1. Field of the Invention
The present invention relates to an inductor used in a semiconductor integrated circuit (IC), and more particularly, to a spiral inductor having a parallel-branch structure.
2. Description of the Related Art
FIG. 1 is a perspective view showing an example of a conventional spiral inductor and FIG. 2 is a plan view of the conventional spiral inductor shown in FIG. 1.
Referring to FIGS. 1 and 2, the spiral inductor 100 includes a first metal line 110 and a second metal line 120. Although not shown, the first and second metal lines 110 and 120 are vertically spaced apart from each other by an insulating layer (not shown) and are connected to each other by a via contact 130 passing through the insulating layer. The second metal line 120 disposed over the insulating layer spirally turns inward from the outer periphery to the center.
Since there is no inductance between the first and second metal lines 110 and 120 in the above-described spiral inductor 100, the number, shape and size of the second metal line 120 must be changed in order to increase the overall inductance. In this case, however, an increase in the size of the inductor is resulted, reducing the overall integration level. Also, when the inductor has a predetermined area or greater, the overall inductance is not increased any longer due to an increase in the parasitic capacitance between the inductor and the underlying substrate. Also, the quality (Q) factor of the inductor is sharply decreased due to parasitic capacitance components with respect to the substrate of the first and second metal lines 110 and 120, which makes it impossible for the inductor to function properly. Further, the maximum Q factor of the inductor is not generated at a desired frequency but is generated at a predetermined frequency.
FIG. 3 is a perspective view showing another example of a conventional spiral inductor and FIG. 4 is a plan view of the conventional spiral inductor shown in FIG. 3.
Referring to FIGS. 3 and 4, a spiral inductor 200 includes a first metal line 210 and a second metal line 220 vertically spaced apart from each other by an insulating layer (not shown). The first and second metal lines 210 and 220 are connected to each other through a via contact 230. Here, at least two first metal lines 210 connected to the via contact 230 are disposed to be parallel. Thus, in addition to the inductance due to the second metal line 220, mutual conductance between the parallel first metal lines 210 is also generated, thereby increasing the overall inductance. Also, a decrease in the overall area of the first metal lines 210 reduces a parasitic capacitance between the inductor and the underlying substrate, leading to an increase in Q-factor. In addition, symmetric arrangement of metal lines facilitates an architecture work of a circuit.
In this case, however, although the overall capacitance is rather increased, the increment in capacitance is negligible. Also, the maximum Q factor is still exhibited at a specific frequency rather than a desired frequency.
Further, various methods of increasing the cross-sectional areas of metal lines have been proposed, including, for example, making a metal line thicker by further providing the plating step, making a three-dimensional shape using bonding wires, forming multiple-layer metal lines of 3 or more layers to then connect the second and third metal lines through many via contacts, and so on. These methods have several manufacturing disadvantages, for example, a lack in reproducibility, a lack in compatibility with silicon based semiconductor processes, an increase in manufacturing cost, a prolonged manufacturing time and so on.
To solve the above-described problems, it is an object of the present invention to provide a spiral inductor having a parallel-branch structure which can be controlled to generate the maximum Q-factor at a desired frequency while increasing the overall inductance and Q-factor without increasing the area occupied by metal lines.
To accomplish the above object, there is provided a spiral inductor having a lower metal line and an upper metal line with an insulating layer interposed therebetween, the lower and upper metal lines being connected to each other through a via contact passing through the insulating layer, wherein the upper metal line spirally turns inward from the periphery to the center, and the lower metal line includes a first lower metal line crossing the upper metal line and disposed to be parallel with another adjacent first lower metal line, and a second lower metal line disposed to be parallel with the upper metal line.
Preferably, the first lower metal line is relatively shorter than the second lower metal line.
The upper and lower metal lines may be electrically parallel connected to each other through the via contact.
The area of the lower metal line is preferably determined by a predetermined frequency at which the maximum Q-factor is exhibited.